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Memory Ordering in CPUs
(
fgiesen.wordpress.com
)
68 points
by
ibobev
21 days ago
|
past
|
7 comments
Memory Ordering in CPUs
(
fgiesen.wordpress.com
)
3 points
by
Tomte
21 days ago
|
past
Memory Ordering in CPUs
(
fgiesen.wordpress.com
)
21 points
by
matt_d
22 days ago
|
past
|
3 comments
Ryg_rans Is Not a Library
(
fgiesen.wordpress.com
)
8 points
by
ibobev
44 days ago
|
past
|
2 comments
PivCo-Huffman "Merge" Operations
(
fgiesen.wordpress.com
)
3 points
by
ibobev
86 days ago
|
past
PivCo-Huffman “merge” operations
(
fgiesen.wordpress.com
)
43 points
by
luu
86 days ago
|
past
|
4 comments
Pinning down a hardware bug in Intel 13th/14th gen CPUs
(
fgiesen.wordpress.com
)
2 points
by
fanf2
3 months ago
|
past
|
1 comment
Why does ASTC use ISE when almost nothing else does?
(
fgiesen.wordpress.com
)
3 points
by
ibobev
3 months ago
|
past
Metaprogramming for Madmen (2012)
(
fgiesen.wordpress.com
)
3 points
by
tosh
3 months ago
|
past
Exact UNORM8 to Float
(
fgiesen.wordpress.com
)
7 points
by
firephox
3 months ago
|
past
|
1 comment
Simple batch decoding of unary codes
(
fgiesen.wordpress.com
)
2 points
by
ibobev
3 months ago
|
past
Why does ASTC use ISE when almost nothing else does?
(
fgiesen.wordpress.com
)
3 points
by
croottree
3 months ago
|
past
Oodle 2.9.14 and Intel 13th/14th gen CPUs (2025)
(
fgiesen.wordpress.com
)
1 point
by
tosh
3 months ago
|
past
Content Creator
(
fgiesen.wordpress.com
)
2 points
by
pocksuppet
6 months ago
|
past
Thoughts on the Witness (2016)
(
fgiesen.wordpress.com
)
2 points
by
Tomte
6 months ago
|
past
Metaprogramming for Madmen (2012)
(
fgiesen.wordpress.com
)
2 points
by
Tomte
6 months ago
|
past
A trip through the Graphics Pipeline (2011)
(
fgiesen.wordpress.com
)
37 points
by
kruuuder
9 months ago
|
past
|
5 comments
Content Creator
(
fgiesen.wordpress.com
)
4 points
by
nice_byte
11 months ago
|
past
A whirlwind introduction to dataflow graphs (2018)
(
fgiesen.wordpress.com
)
37 points
by
shoo
11 months ago
|
past
Why do CPUs have multiple cache levels? (2016)
(
fgiesen.wordpress.com
)
2 points
by
redbell
11 months ago
|
past
Why do CPUs have multiple cache levels?
(
fgiesen.wordpress.com
)
3 points
by
hasheddan
11 months ago
|
past
Ceiling division and mip map sizes
(
fgiesen.wordpress.com
)
2 points
by
luu
11 months ago
|
past
Reading bits in far too many ways (part 1)
(
fgiesen.wordpress.com
)
2 points
by
zmodem
12 months ago
|
past
Content Creator
(
fgiesen.wordpress.com
)
2 points
by
ibobev
on July 7, 2025
|
past
Oodle 2.9.14 and Intel 13th/14th gen CPUs
(
fgiesen.wordpress.com
)
6 points
by
Shinobuu
on June 11, 2025
|
past
|
1 comment
Oodle 2.9.14 and Intel 13th/14th gen CPUs
(
fgiesen.wordpress.com
)
4 points
by
frogblast
on May 22, 2025
|
past
Oodle 2.9.14 and Intel 13th/14th gen CPUs
(
fgiesen.wordpress.com
)
16 points
by
matt_d
on May 22, 2025
|
past
|
1 comment
Row major vs. column major arrays, row vectors vs. column vectors (2012)
(
fgiesen.wordpress.com
)
1 point
by
fanf2
on March 6, 2025
|
past
The double MMAP() magic ring buffer (2012)
(
fgiesen.wordpress.com
)
1 point
by
fanf2
on Feb 7, 2025
|
past
Unorm and SNORM to float, hardware edition
(
fgiesen.wordpress.com
)
31 points
by
luu
on Dec 24, 2024
|
past
|
9 comments
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